| 1. | Efficient execution of multiple queries on deep memory hierarchy
多存储层次中多个查询的高效执行 |
| 2. | Design and realization of memory hierarchy based on tms320c6711 processor
6711处理器的存储体系设计与实现 |
| 3. | The value of a small microkernel for dreamy memory and the rampage memory hierarchy
梦幻存储器小微核的价值与rampage存储层次 |
| 4. | All systems have a memory hierarchy with memory at different speeds and sizes at different points in the hierarchy
所有计算机系统都有一个由不同速度与大小的存储器组成的层次结构。 |
| 5. | 29 zhang y , chen z , zhou y . efficient execution of multiple queries on deep memory hierarchy full version
本文下一步需要考虑的是， minitasking如何与现有的数据库管理系统的查询执行引擎相结合。 |
| 6. | The goal of a cache - oblivious algorithm is to be optimal in the use of the memory hierarchy , but without knowing any parameters of the hierarchy
高速缓存参数无关算法的目标是，在不了解任何有关各层次参数的情况下，最优地使用存储系统。 |
| 7. | This paper explores potential for the rampage memory hierarchy to use a microkernel with a small memory footprint , in a specialized cache - speed static ram tightly - coupled memory , tcm
本文探讨了专用的cache同速静态ram紧耦合存储器，简称tcm中rampage存储层次使用一种带有少量存储痕迹的微核的可能性。 |
| 8. | Accessing words in the lower , faster levels of this memory hierarchy can be done virtually immediately , but accessing the upper levels may cause delays of millions of processor cycles
对该层次存储体系中较低且速度较快的层次中字的访问可立即得到响应，而对较高层次的访问可能导致数百万的处理器周期延迟。 |
| 9. | 24 machanick p . correction to rampage asplos paper . computer architecture news , september 1999 , 27 : 2 - 5 . 25 machanick p , patel z . l1 cache and tlb enhancements to the rampage memory hierarchy
仿真是基于适合移动设备的参数进行的，目的是尽可能把dram的能耗降低到自刷新模式能耗，而把把dram的性能提高到全功率模式的性能。 |
| 10. | Architectural support for programming languages and operating systems asplos - viii , san jose , ca , october 1998 , pp . 105 - 114 . 2 machanick p . scalability of the rampage memory hierarchy . south african computer journal , august 2000 , : 68 - 73
以往的工作说明，根据硬软件折衷， rampage是一个潜在可行的方案同时也说明，随着cpu - dram的速度差的增大， rampage也随之适度变化。 |
